• Cadence Cerebrus to Enable Chip Design with ML: PPA Optimization in Hours, not Months

    6 days ago - By Anand Tech

    The design of most leading edge processors and ASICs rely on steps of optimization, with the three key optimization points being Performance, Power, and Area. Once the architecture of a chip is planned, it comes down to designing the silicon of that chip for a given process node technology, however there are many different ways to lay the design out. Normally this can take a team of engineers several months, even with algorithmic tools and simulation to get a good result, however that role is gradually being taken over with Machine Learning methods. Cadence today is announcing its new...
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  • Cadence Design Systems launches Cerebrus machine learning for chip design

    Cadence Design Systems launches Cerebrus machine learning for chip design

    6 days ago - By VentureBeat

    Cadence Design Systems is using machine learning in its Cerebrus Intelligent Chip Explorer tool for designing complex chips.
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